M
Mike Monett
- Jan 1, 1970
- 0
john jardine said:John Larkin wrote:
This was built along similar lines. The synchronous rectification
is not perfect due to phase shift in the forward signal path but
the arrangement is useful for reducing the annoying capacitive
quadrature component from Q's up to about 3 (at the 100kHz). It's
usable down to the milliohm area and proved the (cheap) 1000 off
10uF cap's I bought, had an ESR of between 1 and 3 ohms!.
Hi John,
Do you mind if I make some comments? The 1 ohm resistor, R5, can be
removed from the circuit. It is at a virtual ground node and has
little or no voltage across it. So removing it has little effect on
the circuit.
With R5 gone, and the ESR range switch in the 1 ohm position, the
180 ohm resistor, R4, is effectively in series with the capacitor
under test. The op amp merely changes the location of the ground
node, and inverts the output signal polarity.
Since R4 (180 ohms) is now in series with the capacitor, it
completely swamps out the internal ESR (0.05 ohms.) This means the
series combination of C, L, and R has negligible "Q", and there is
no quadrature or orthogonal component in the circuit.
However, as the ESR decreases, the corresponding voltage drop that
we are trying to measure also decreases. We no are faced with the
problem that the di/dt from the inductor is much larger than the I*R
drop from the ESR. This means the leading and trailing edge of the
square wave have large spikes.
If you used a diode peak detector to measure the amplitude, it would
respond as best it could to the leading edge spike, which would make
it impossible to measure the drop across the ESR. Your circuit and
Larkin's share this problem.
Using a synchronous rectifier helps a bit, but you are now faced
with trying to turn it on after the leading edge spike, and to turn
it off before the trailing edge spike. That could be tricky.
I spent this afternoon looking at these problems in SPICE, and have
come to an amazing observation. There is a hidden but very
significant feature in the bridge ESR circuit referred to at the
beginning of this thread. The links are:
1. Talino Tribuzio's page, showing the circuit from Nuova
Elettronica:
http://www.qsl.net/iz7ath/web/02_brew/15_lab/06_esr/index.htm
2. Gintaras' web page, who refers to Tribuzio's page in his readme
http://alytus.auksa.lt/esr/
The schematic is at
http://alytus.auksa.lt/esr/esr_meter_schematic.pdf
The valuable hidden feature is the bridge configuration completely
eliminates the leading and trailing edge spikes due to the capacitor
internal inductance. Since the spikes are in phase with the square
wave signal on the other side of the bridge, they simply disappear
at the output of the op amp!
This means the peak detector has a very clean square wave to work
with, and it can give a much more accurate measurement of the
signal. There is no tricky timing to fiddle with that can go out of
whack just when you need to use the tester.
If you like, I can post the analysis of your circuit and Larkin's
version showing the huge spikes that appear as the ESR becomes
smaller, and the triangular wave from the capacitance charging and
discharging. I don't really see a good way of overcoming these
problems.
As I mentioned in previous posts, the bridge circuit has significant
advantages, including low test voltage, in-circuit test, shorted
capacitor detect, etc. With the extremely clean output signal into
the peak detector, it becomes the obvious choice for hassle-free ESR
measurements.
I'll post the LTspice ASC file here along with the PLT file so you
can see how it works. I changed the bridge resistance to lower
values to allow measuring lower values of ESR.
Here's the LTspice ASC file:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Version 4
SHEET 1 880 708
WIRE -496 -112 -528 -112
WIRE -368 -112 -416 -112
WIRE -304 -112 -368 -112
WIRE -192 -112 -224 -112
WIRE -368 -96 -368 -112
WIRE -128 -80 -160 -80
WIRE -48 -64 -64 -64
WIRE -720 -48 -816 -48
WIRE -704 -48 -720 -48
WIRE -592 -48 -624 -48
WIRE -528 -48 -528 -112
WIRE -528 -48 -592 -48
WIRE -368 -48 -528 -48
WIRE -192 -48 -192 -112
WIRE -192 -48 -288 -48
WIRE -128 -48 -192 -48
WIRE -816 -32 -816 -48
WIRE -160 0 -160 -80
WIRE -160 0 -240 0
WIRE 128 16 96 16
WIRE 224 32 192 32
WIRE 240 32 224 32
WIRE 336 32 304 32
WIRE -528 48 -592 48
WIRE -240 48 -240 0
WIRE -240 48 -448 48
WIRE -224 48 -240 48
WIRE -96 48 -144 48
WIRE -48 48 -48 -64
WIRE -48 48 -96 48
WIRE 32 48 16 48
WIRE 128 48 32 48
WIRE -816 64 -816 48
WIRE 32 128 32 48
WIRE -720 144 -720 -48
WIRE -704 144 -720 144
WIRE -592 144 -592 48
WIRE -592 144 -624 144
WIRE -512 144 -592 144
WIRE -416 144 -448 144
WIRE -304 144 -336 144
WIRE -192 144 -224 144
WIRE -592 160 -592 144
WIRE -192 160 -192 144
WIRE 96 176 96 16
WIRE 208 176 96 176
WIRE 336 176 336 32
WIRE 336 176 208 176
WIRE 208 192 208 176
WIRE 336 208 336 176
WIRE 32 224 32 208
WIRE -592 256 -592 240
WIRE -464 272 -480 272
WIRE -432 272 -464 272
WIRE -272 272 -288 272
WIRE -240 272 -272 272
WIRE -480 288 -480 272
WIRE -288 288 -288 272
WIRE 208 288 208 272
WIRE 336 288 336 272
WIRE -480 384 -480 368
WIRE -288 384 -288 368
FLAG -96 48 DIFF
FLAG -592 256 0
FLAG -192 160 0
FLAG -816 64 0
FLAG -368 -96 0
FLAG -592 -48 E2P
FLAG -592 48 E2N
FLAG 32 224 0
FLAG 336 288 0
FLAG 208 288 0
FLAG 336 32 DC
FLAG -480 384 0
FLAG -464 272 VCC
FLAG -288 384 0
FLAG -272 272 VEE
FLAG 224 32 VOP
FLAG 32 48 VIN
FLAG 160 0 VCC
FLAG 160 64 VEE
FLAG -96 -96 VCC
FLAG -96 -32 VEE
SYMBOL res -608 144 R0
SYMATTR InstName R8
SYMATTR Value {Rb}
SYMBOL res -608 128 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R9
SYMATTR Value {Rt}
SYMBOL cap -448 128 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C3
SYMATTR Value {C}
SYMBOL res -320 128 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R10
SYMATTR Value {ERS}
SYMBOL ind -320 160 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName L3
SYMATTR Value {L}
SYMBOL Voltage -816 -48 R0
WINDOW 0 42 44 Left 0
WINDOW 3 -22 -62 Left 0
WINDOW 123 15 130 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 4 0 {Tr} {Tr} 5u 10u)
SYMBOL res -608 -64 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value {Rt}
SYMBOL res -512 -96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R11
SYMATTR Value {Rb}
SYMBOL res -320 -96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R12
SYMATTR Value 47k
SYMBOL res -384 -32 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R13
SYMATTR Value 1k
SYMBOL res -544 64 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R14
SYMATTR Value 1k
SYMBOL res -240 64 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R15
SYMATTR Value 47k
SYMBOL cap 16 32 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C4
SYMATTR Value 2n
SYMBOL res 16 112 R0
SYMATTR InstName R16
SYMATTR Value 47k
SYMBOL diode 240 48 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL cap 320 208 R0
SYMATTR InstName C5
SYMATTR Value 2nf
SYMBOL res 192 176 R0
SYMATTR InstName R17
SYMATTR Value 470k
SYMBOL Opamps\\1pole 160 32 R0
SYMATTR InstName U1
SYMATTR Value2 Avol=1Meg GBW=100Meg Slew=100Meg
SYMBOL Voltage -480 272 R0
WINDOW 0 42 44 Left 0
WINDOW 3 47 72 Left 0
WINDOW 123 15 130 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL Voltage -288 384 R180
WINDOW 0 42 44 Left 0
WINDOW 3 47 72 Left 0
WINDOW 123 15 130 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL Opamps\\1pole -96 -64 R0
SYMATTR InstName U2
SYMATTR Value2 Avol=1Meg GBW=100Meg Slew=100Meg
TEXT -528 -224 Left 0 ;'Tribuzio Bridge ESR Circuit
TEXT -528 -184 Left 0 !.tran 0 2.2m 2m 100n
TEXT 32 -200 Left 0 !.param C = 100uF\n.param L = 2.533E-08\n.param ERS =
0.00005\n.param Rt = 100\n.param Rb = 1\n.param Tr = 100n
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Here's the PLT file:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[Transient Analysis]
{
Npanes: 3
Active Pane: 1
{
traces: 1 {268959746,0,"V(dc)"}
X: ('µ',0,0,2e-005,0.0002)
Y[0]: (' ',3,0,0.003,1)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: (' ',0,0,0,0,0.003,1)
Log: 0 0 0
GridStyle: 1
},
{
traces: 1 {268959747,0,"V(diff)"}
X: ('µ',0,0,2e-005,0.0002)
Y[0]: (' ',1,-1,0.2,1)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: (' ',0,0,2,-1,0.2,1)
Log: 0 0 0
GridStyle: 1
},
{
traces: 1 {268959748,0,"V(e2n)"}
X: ('µ',0,0,2e-005,0.0002)
Y[0]: ('m',0,0,0.002,0.04)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: ('m',0,0,0,0,0.002,0.04)
Log: 0 0 0
GridStyle: 1
}
}
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Regards,
Mike Monett