OK, here we go.
The transmitter and receiver are independent but I've shown them both on the same timing diagram for convenience, with the transmitter's signals at the top and the receiver's signals at the bottom, and the transmitted data stream in the middle, labelled TXD and RXD straddling the dividing line. This data stream is generated continuously by the transmitter.
This signal is normally high. At the start of the frame, it goes low for one bit time (called the "start bit"), then the seven data bits are transmitted, low bit first, then the signal returns high. This is the way asynchronous serial data is normally transmitted, and this signal can be received by the UART (universal asynchronous receiver/transmitter) in a standard microcontroller.
After the start bit and the data bits, there is an idle period eight bits long. This ensures that the receiver has stopped receiving and is ready to detect a new start bit; without this delay, the receiver could get out-of-sync and interpret 0-bits in the data as start bits.
The transmitter runs continuously, generating this data stream constantly. Timing is controlled by TU2, a 74HC4020 ripple-carry binary counter, which is clocked at 32768 Hz from a crystal-controlled oscillator built around TU1A, a NAND gate used as an inverter.
The 74HC4020 consists of fourteen cascaded "T" flip-flops - logical blocks that toggle their output from low to high, or from high to low, when they receive a particular edge on their inputs. In this case, they are triggered by falling edges, i.e. high-to-low transitions. Because each cycle (rising edge then falling edge) at the input causes a half cycle at the output (just a rising edge, or just a falling edge), each T flip-flop divides its input frequency by 2, i.e. the frequency at its output is half the frequency at its input.
The first T flip-flop in the 74HC4020 is clocked from the clock input pin at 32768 Hz. Its output frequency is 16384 Hz, and it is called Q1. Q1 clocks the second flip-flop, whose output, Q2, at 8192 Hz, is not brought out to a pin. It clocks the third flip-flop, whose output, Q3, at 4096 Hz, is also not brought out to a pin. It clocks the fourth flip-flop, whose output is Q4, 2048 Hz, and so on. From Q4 up to Q14, the flip-flop outputs are brought out to pins on the 74HC4020, and two of them are used for timing in the transmitter.
You can see this frequency division in the first five lines of the timing diagram, which show the Q10, Q11, Q12, Q13 and Q14 outputs of TU2. (Only Q10 and Q14 are actually used in the circuit.) On every falling edge (high to low transition) on Q10, Q11 changes state. If it was low, it goes high. If it was high, it goes low. I've drawn some red arrows to show you how a falling edge on one signal causes an edge on the next signal. These signals run continuously.
The bit rate is determined by which Qn output is connected to TU1D and becomes the TBC (transmit bit clock) signal. In this design I have used Q10, which has a frequency of 32 Hz. This produces a transmitted data rate of 32 bits per second (bps). Since a transmit frame consists of 16 bit-periods, the transmitter will transmit two frames per second.
The TFC (transmit frame clock) signal MUST be taken from the Q output (on TU2) that is four numbers higher than the signal that feeds TU1D. Since TU1D is fed from Q10, TFC must come from Q14. If you want to increase the bit rate (and therefore the update rate), you can use Q9 and Q13 (64 bps, four frames per second), Q8 and Q12 (128 bps, 8 frames per second), and so on.
The next signal in the timing diagram is TSH, Transmit SHift. It is taken from TFC with a short delay provided by TR3 and TC3. The delay is indicated on the timing diagram. The actual duration of the delay is not very critical; it is just needed to overcome propagation delays in the logic ICs, so anything longer than a few microseconds is plenty.
The last transmitter signal is TBC, the transmit bit clock, which is an inverted copy of the Q10 output from TU2. This signal is named TBC and also Q10 with an overbar; the overbar means "inverted". Some of the rising edges on this signal are marked with arrows because this signal is used as a clock source for TU3, the shift register, and TU3 responds to rising edges on its clock input.
TU3 is a 74HC165 "serial/parallel input, serial output shift register". It consists of a chain of flip-flops, kind of like the 74HC4020, but these are not cascaded toggle flip-flops; they are a "shift register". All of the flip-flops are clocked from the clock input (which is fed with the TBC signal). When the shift register is in "shift" mode, each rising edge on TBC will "shift" the data along the chain of flip-flops. Each flip-flop will load, and latch, the state of the previous flip-flop in the chain. The output of the last flip-flop is brought out on the QH signal on pin 9, and in inverted form on pin 7.
The other function of the shift register is parallel load. The TSH (transmit shift) signal drives pin 1, the SHIFT/-LOAD input of the shift register. While this signal is low, the shift register keeps the flip-flops following the levels on the pins named A to H. Clock edges from TBC have no effect while TSH is low. Clocking of the data through the shift register can only occur when TSH is high.
Now we have enough information to understand the transmitter. Let's start at the point labelled START OF FRAME in the timing diagram. This point corresponds to falling edges on Q10, Q11, Q12 and Q13, and a rising edge on Q14/TFC.
Prior to the start of frame, TSH is low so TU3 is in load mode, and its flip-flops are held at the same states as the A~H inputs. The last flip-flop in the shift register chain is called flip-flop H and its output is made available on pin 9, named QH, and in inverted form, on pin 7, named QH with an overbar (overbar means inverted). The H input is tied low, so during load mode, pin 9 will be low and pin 7 will be high.
When TFC goes high, both of TU1B's inputs are high, so its output goes low (NAND function). This produces the falling edge on TXD at the beginning of the start bit.
A short time later, this high level on TFC propages through the short delay provided by TR3 and TC3, and TSH goes high. TU3 is now in shift mode, and subsequent rising edges on TBC will clock the data that was loaded into the flip-flops in the shift register from the A~H inputs during the "load" period.
One bit-period into the frame, Q10 goes low and TBC (an inverted version of Q10) goes high. This is the first transition on TBC that is marked with an arrow; this indicates that this rising edge will clock the shift register inside TU3. The data is shifted along one bit, towards the QH output. The previous state of QH, which came from the H input, is lost, and replaced by the state from the TD0 signal. Since TFC is still high, TU1B acts as an inverter and reproduces the QH state (inverted QH going through an inversion stage) at its output, TXD.
This process continues through the first half of the frame. On each rising edge of TBC, the data in the shift register shifts along by one bit, and another bit of the parallel incoming data is shifted to the output on QH and transmitted.
After the seventh data bit (D6) has been transmitted, TFC goes low, which forces TU1B's output high for the remainder of the frame. Then the process repeats indefinitely. The transmitted data is as shown - one start bit, followed by seven bits of data, followed by eight bit-times of idle line (high signal). This data can be received by a standard UART set for one start bit, seven or eight bits of data, no parity, and one stop bit. If the UART is set to receive eight data bits, the most significant bit, bit 7, will always be received as a 1.
The receiver is similar but uses some extra logic to detect the start bit and come out of idle mode. It also uses a 74HC4020 clocked at 32768 Hz but in the receiver, the reset input of the 74HC4020 is used. It is driven from a signal called RCR, "receiver counter reset". While RCR is high, all of the cascaded toggle flip-flops in the divider chain in the 74HC4020 are held in the reset state, so all of the Qn outputs are held low. Once RCR goes low, the 74HC4020 begins counting.
Initially, RXI (receiver idle) is high, and the receiver is idle. The receiver's first task is to detect the start bit. This is done using RU2, the 74HC4020 counter IC, which is held reset by the RCR signal, driven by RU3B, which is high because RXD and RXI are both high. When RXD goes low at the start of the start bit, RCR goes low as well, and RU2 starts to count. If the low state remains present on RXD, after half a bit time, RBC/Q10 will go high. This is shown on the timing diagram with a blue arrow, because RCR going low enables RU2 to start counting but RBC doesn't go high until it has counted half of a bit-time, so one causes the other, but with a delay.
If the low state on RXD is shorter than half a bit time, e.g. noise on the line, RCR will go high before RBC goes high, RCR will return high, and nothing more will happen until a low state of at least half a bit-time is detected on RXD.
RU1A and RU1D are cross-connected NOR gates that form a set/reset (SR) flip-flop with inputs on pins 12 and 3. Once RBC goes high, this latch flips to the opposite state, and RXI goes low. The receiver is no longer idle. RXI being low forces RCR to remain low, so RU2 can continue to count regardless of the state of RXD.
Now with RXI low, rising edges on RBC clock the RXD state into RU4, which contains a shift register like the one in the transmitter, but it is used differently. In RU4, a 74HC595, there is only one input to the shift register, called the "serial input" on pin 14. Like the 74HC165 in the transmitter, it has eight flip-flops named A~H which are clocked simultaneously by rising edges on pin 11 (the RBC signal). On each clock, data is shifted along the shift register so the state that was in flip-flop A is now in flip-flop B, and the state that was in flip-flop B is now in flip-flop C, and so on. The data that was in flip-flop H is lost, and the new data in flip-flop A comes from the serial input on pin 14.
So the first rising edge on RBC actually clocks the start bit state, which is always 0, into the shift register. Subsequent rising edges on RBC clock the states of D0, D1, D2, D3, D4, D5 and D6 into the shift register, leaving the state of D6 in flip-flop A. This method of sampling the RXD signal once per bit, in the centre of the bit, is simpler and less robust than the method used by UARTs, which sample at least three times per bit , often as many as eight, and decide on the bit value according to which state (high or low) occurred for more samples.
At the end of the frame, a number of things occur in rapid succession. This is shown by the tangled mess of red arrows in this section of the timing diagram.
When RU2 has been counting for eight bit periods, a ripple-through occurs when Q10 goes low. This causes Q11 to go low, which causes Q12 to go low, which causes Q13 to go low, which causes Q14/RFC to toggle - in this case it was previously low, so it goes high.
As soon as this happens, the set/reset latch formed by RU1A and RU1D flips back to its original state, and RXI goes high. Since RXD is also high at this point, RCR goes high and RU2 resets, and all of its Q outputs go low. This process is indicated by the red lines and arrows in the timing diagram.
When RXI goes high, the rising edge on pin 12 of RU4 causes the states of the eight shift register flip-flops to be transferred simultaneously to another set of eight flip-flops inside RU4. These flip-flops actually drive the QA~QH output pins. I hadn't mentioned them before. But they are there so that data can be clocked into the shift register over a period of time, then transferred instantly to the outputs. This prevents the outputs from changing constantly as the data is clocked through the shift register section and provides stable, clean outputs on RD6~RD1.
At the time when RXI goes high, data bit D6 has just been clocked into flip-flop A in RU4. Older data (D5, D4, D3, D2, D1, D0, and the start bit) are in flip-flops B~H.
Now that the receiver is back in the idle state, it waits for a new start bit and the process repeats.
Obviously, the receiver's bit rate must match the transmitter's bit rate. Like I did for the the transmitter, I have used a bit rate of 32 bps, giving two frames (updates) per second. But as for the transmitter, you can increase the bit rate by taking the RBC signal from a lower-numbered Qn output on RU2, as long as the RFC signal is taken from the Qn output that is four higher than the one you use for RBC.
I haven't simulated this circuit, but I have gone through it step by step in this explanation so I'm pretty confident that it will work. You are welcome to simulate it, of course, and/or build and test it. I had a look at options for simulation but all of the free ones were designed as educational tools and did not include models of the 74HC4020 or the two shift register ICs.
The schematic doesn't show the power connections to the logic gate ICs, nor to the 74HC4020s. You have to make those connections. Also, each IC, especially the counters and shift registers, must have a decoupling capacitor such as a 0.1 µF ceramic connected between its VDD and VSS pins as close as possible to the IC.
Although the transmitter generates completely standard asynchronous serial data (apart from the fact that there are only seven bits of data, which is a bit unusual nowadays), the receiver does not use the normal sampling techniques used by UARTs in PC serial ports and microcontrollers. The main differences are in how a start bit is detected (this receiver requires RXD to be low continuously for half a bit-time) and how the data bit states are detected (this receiver takes a single sample in the middle of the bit-time).
There is no error checking and any line disturbance can confuse the receiver and cause incorrect data to be displayed.
If the data stops, for any reason, and RXD is stuck high, the receiver will simply stop updating its outputs, without any indication of this fact. If some kind of activity indicator is required, you could connect an LED (with a suitable series resistor) from the Q13 output on RU2 to 0V. This LED would remain OFF if no data is arriving, but will blink rapidly while data is being received.