We've had - so far - 100% success with pre-assigning the pins on
Xilinx chips to optimize pcb layout. But the fastest we've clocked is
77 MHz, and that's not screaming these days.
I did 200MHz in a Virtex-E assigning pins to optimize the PCB (I/Os
directly adjacent to the driving/driven chip). I figured that the PCB
timing was a worse problem than the FPGA routing resources. ..besides,
I had to start somewhere. ;-)
That makes me shiver just to think about it. What needs such density?
'90s mainframe processor and channel boards.
And how much does such a bare board cost?
I never saw the costs, and would be suspect of any costs I did see.
The widget they're going in sold for upwards of $25M (six or eight
processors, with all the chrome and channels ;.
100 layers must have interesting impedance and signal-quality issues.
How thick?
I don't remember the thickness. I only worked on one side. ;-)
Impedance was very tightly controlled though. High speed board-to-
board wiring was either done in Gore-Tex trilead (G-S-G sort of
twinlead) or coax. ...all 80ohm, IIRC.
Only rarely, in a critical timing bit, usually to meet pin-pin prop
delay requirements, not to get it to work as such. But usually we play
with the design (pipelining, logic depth, fanouts) to get the speed we
need.
That's I/Os. How about the logic inside? ;-) I loan myself out to the
timing group sometimes when I have less to do than I want. The design
is done, "your job, should you choose to accept" is to defy the
synthesis tools and make timing, using nothing but bubblegum and fence
wire.
Not in my life, thank goodness.
They still are, except the complication has moved somewhat from density
(that goes on the chips) to timing and skew analysis. With busses
humping along at 1GHz (in consumer products, even), there isn't much
slop thrown in for these things. I'm amazed that PCs work at all.
